1. Field of the Invention
The present invention is related to a digital filter. Particularly, the present invention relates to a technique of preventing overflow oscillation appearing in a digital biquad filter.
2. Prior Art
In the recent years, digital filters have been broadly utilized in electronic appliances while A/D (analog to digital) converters on the basis of an oversampling scheme have become more prevalent. Particularly, biquad filters are selectively used in many cases since these filters have lower sensitivities to the coefficient variation and therefore the operation is highly stabilized.
The analog to digital converter on the basis of an oversampling scheme serves to convert analog input signals with a sampling rate which is by far higher than the highest frequency component of the analog input signals, and pass the digital output signals as converted through a digital low-pass filter which is located in a later stage in order to attenuate the noise level at high frequencies and lessen conversion noise. Particularly, in the case of the type on the basis of the ΔΣscheme, the conversion noise has a frequency characteristic so called as the noise shaping in which the power spectrum of noise is deflected to the high frequency area so that, even when converted to one-bit digital signals, it is possible to secure the accuracy of the order of 14 bits by oversampling. Accordingly, it is possible to reduce the area ratio of an LSI (large scale integrated circuit) as occupied by the constituent analog circuitry in the entirety LSI chip and also simplify the configuration of the analog circuitry itself so that this type of A/D converter for which the digital filtering is necessary has been employed in mobile phones and so forth.
The kinds of such electronic appliances tends to be designed to improve the operability and the multiple functional feature in addition to the basic functions so that it is desirable to reduce the circuit area required for implementing a digital filter in the LSI chip. With respect to the need for reducing the circuit area, the serial calculation scheme provides a particularly excellent area utilization efficiency.
However, in accordance with this scheme, it is difficult to detect overflows and also handle the overflows even detected. The overflow occurs when the magnitude of a calculation result exceeds the predetermined bit length of a digital data processing apparatus. In the case of the serial calculation scheme, the processing operation is sequentially advanced bit by bit from the LSB (least significant bit) to the MSB (most significant bit). In this case, the overflow can be detected only after the MSB is processed so that less significant bits has been already output from an arithmetic unit when detected.
FIG. 40(a) and FIG. 40(b) are graphic diagrams respectively showing an input signal waveform and an output signal waveform in the case where overflow takes place in a digital biquad filter.
Unlike the responses of analog circuits, the output signal is violently vibrated in response to the excessive input signal. This phenomenon is called an overflow oscillation.
The overflow oscillation is originating from the fact that digital signals are processed with two's complement arithmetic. For example, the numbers from −4 to +3 are represented in accordance with the two's complement system as follows.
+3:011+2:010+1:0010:000−1:111−2:110−3:101−4:100
Usual decimal number representations are located on the left hand side of the colon (:) while the corresponding number representations in accordance with the two's complement system are located on the right hand side. The number +3 as incremented by one is +4 to be represented by (0100) in accordance with the two's complement system. However, since there are only three bits as available, the number +3 is incremented as −4(100), −3(101) and −2(110). Also, the number −4 as decremented by one is −5 to be represented by (1011) in accordance with the two's complement system. However, since there are only three bits as available, the number −4 is decremented as +3(011), +2(010) and +1(001).
For this reason, there are output waves oscillating between values in the vicinity of the positive representation limit and values in the vicinity of the negative representation limit as illustrated in FIG. 40(b) when the output goes to and comes back from the overflow state.
FIG. 37 is a circuit diagram showing a prior art digital biquad filter (inside of the broken line) in accordance with the serial calculation scheme for suppressing the overflow oscillation.
In the figure, the reference numerals 1a and 1d designate 1-bit registers respectively; the reference numerals 1b, 1c, 1eand 1f designate shift registers respectively capable of latching and shifting a plurality of bits; the reference numeral 2 designates a coefficient multiplication circuit; the reference numeral 3 designates an adder circuit; the reference numeral 4 designates an exclusive NOR gate (the matching circuit); the reference numeral 5 designates a selector circuit; and the reference numeral 6 designates an AND gate. FIG. 38 is a circuit diagram showing an example of a selector circuit used in a digital filter. In FIG. 37, control signals to be given to the selector circuit is dispensed with in the illustration.
Biquad circuits are connected in series in many cases so that some elements of a previous and a subsequent biquad circuit are illustrated in FIG. 37. The shift registers 1e and 1f are inserted for the purpose of compensating the delay time of the coefficient multiplication circuit 2 and therefore can be dispensed with if the delay time of the coefficient multiplication circuit is no longer than one operation cycle.
The prior art digital biquad filter is provided with a circuit for preventing overflow oscillation which is similar as disclosed in FIG. 4 of IEEE Journal of Solid-State Circuits, vol. SC-23, no. 3, p. 838, comprises an exclusive NOR (OR) gate 4 and the AND gate 6 and serving to clamp the internal value as latched by the shift register to a value of “0” when overflow is detected.
This operation is implemented with the exclusive NOR gate 4, the selector circuit 5, the 1-bit register 1d and the AND gate 6. At a time as the exclusive NOR gate 4 detects whether or not the MSB matches the adjacent lower bit, the selector circuit 5 outputs the result of the matching to the 1-bit register 1d which latches the result in the next operation cycle. The result of detection is “1” (match) is indicative of a normal operation while the result of detection is “0” (mismatch) is indicative of an overflow. While the output signal of the shift register 1b or 1c is output from the AND gate 6 as it is in the normal operation, the output signal of the AND gate 6 becomes always “0” in the case of an overflow. FIG. 39(a) and FIG. 39(b) are graphic diagrams respectively showing an input signal waveform and an output signal waveform in the case where overflow takes place in the prior art digital biquad filter as illustrated in FIG. 37. As seen from FIG. 39(a) and FIG. 39(b), it will be understood that there takes place yet some overflow oscillation and that a number of noise spikes in response to input signals in the vicinity of the overflow limit.
Accordingly, there are following two shortcomings in the prior art digital biquad filter.
The first shortcoming is that an exclusive NOR (OR) gate can not be used to detect overflow extending beyond two or more bits (for example, large steps as illustrated in FIG. 39(b)). Four addition operations are performed by the circuit as illustrated in FIG. 37 including the biquad circuit of the previous stage during one cycle of operation. Even in the case where the multiply operation invokes no overflow, an overflow of three bits is possible.
The second shortcoming is that it is impossible to completely remove overflow oscillation (small spikes appearing in the waveform as illustrated in FIG. 39(b)). When overflow is detected, the signals including the overflow data have already been output. Also, since the internal value is clamped to “0”, when the operation is switched between the normal operation and the overflow preventing operation, there are generated steps in the waveform as noise signals.
The present invention has been made in order to solve the conventional shortcomings as described above. It is an object of the present invention to provide a digital filter having the capability to prevent the digital filter from generating the overflow oscillation by detecting positive and negative overflows propagating one or a plurality of bits.